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? 2007 microchip technology inc. ds21730f-page 1 mcp201 features ? supports baud rates up to 20 kbaud ? 40v load dump protected ? wide supply voltage, 6.0 ? 18.0v, continuous - maximum input voltage of 30v ? extended temperature range: -40c to +125c ? interface to standard usarts ? compatible with lin spec 1.3 ? local interconnect network (lin) line pin: - internal pull-up resistor and diode - protected against ground shorts (lin pin to ground) - protected against lin pin loss of ground - high current drive, 40 ma i ol 200 ma ? automatic thermal shutdown ? on-board voltage regulator: - output voltage of 5v with 5% tolerances over temperature range - maximum output current of 50 ma - able to drive an external series-pass transistor for increased current supply capability - internal thermal overload protection - internal short-circuit current limit - external components limited to filter capacitor only and load capacitor package types block diagram mcp201 pdip, soic, dfn 8 7 6 5 1 2 3 4 rxd cs/wake v reg txd fault /slps v bat lin v ss voltage regulator ratiometric reference oc thermal protection internal circuits v reg fault /slps rxd txd v bat lin vss approx. cs/wake wake-up logic slope control por 30 k lin transceiver with voltage regulator
mcp201 ds21730f-page 2 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21730f-page 3 mcp201 1.0 device overview the mcp201 provides a physical interface between a microcontroller and a lin half-duplex bus. it is intended for automotive and industrial applications with serial bus speeds up to 20 kbaud. the mcp201 provides a half-duplex, bidirectional communications interface between a microcontroller and the serial network bus. this device will translate the cmos/ttl logic levels to lin level logic, and vice versa. the lin specification 1.3 requires that the transceiver of all nodes in the system be connected via the lin pin, referenced to ground and with a maximum external termination resistance of 510 from lin bus to battery supply. the 510 corresponds to 1 master and 16 slave nodes. the mcp201 provides a +5v 50 ma regulated power output. the regulator uses a ldo design, is short- circuit-protected and will turn the regulator output off if it falls below 3.5v. the mcp201 also includes thermal shutdown protection. the regulator has been specifi- cally designed to operate in the automotive environ- ment and will survive reverse battery connections, +40v load dump transients and double-battery jumps (see section 1.6 ?internal voltage regulator? ). 1.1 optional external protection 1.1.1 transient voltage protection (load dump) an external 27v transient suppressor (tvs) diode, between v bat and ground, with a 50 resistor in series with the battery supply and the v bat pin, serves to pro- tect the device from power transients (see figure 1-2) and esd events. while this protection is optional, it should be considered as good engineering practice. 1.1.2 reverse battery protection an external reverse-battery-blocking diode can be used to provide polarity protection (see figure 1-2). this protection is optional, but should be considered as good engineering practice. 1.2 internal protection 1.2.1 esd protection for component-level esd ratings, please refer to the maximum operation specifications. 1.2.2 ground loss protection the lin bus specification states that the lin pin must transition to the recessive state when ground is disconnected. therefore, a loss of ground effectively forces the lin line to a hi-impedance level. 1.2.3 thermal protection the thermal protection circuit monitors the die temperature and is able to shut down the lin transmitter and voltage regulator. refer to table 1-1 for details. there are three causes for a thermal overload. a thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions. ? voltage regulator overload ? lin bus output overload ? increase in die temperature due to increase in environment temperature driving the txd and checking the rxd pin makes it possible to determine whether there is a bus contention (rx = low, tx = high) or a thermal overload condition (rx = high, tx = low). table 1-1: sources of thermal overload (1,2) note: after recovering from a thermal, bus or voltage regulator overload condition, the device will be in the ready1 mode. in order to go into operational mode, the cs/ wake pin has to be toggled. txd rxd comments l h lin transmitter shutdown, receiver and voltage regulator active, thermal overload condition. h l regulator shutdown, receiver active, bus contention. legend: x = don?t care, l = low, h = high note 1: lin transceiver overload current on the lin pin is 200 ma. 2: voltage regulator overload current on voltage regulator greater than 50 ma.
mcp201 ds21730f-page 4 ? 2007 microchip technology inc. 1.3 modes of operation for an overview of all operational modes, please refer to table 1-2. 1.3.1 power-down mode in the power-down mode, the transmitter and the voltage regulator are both off. only the receiver section and the cs/wake pin wake-up circuits are in operation. this is the lowest power mode. if any bus activity (e.g., a break character) should occur during power-down mode, the device will immediately enable the voltage regulator. once the output has stabilized, the device will enter ready mode. the part will enter the operation mode, if the cs/wake pin should become active-high (? 1 ?). 1.3.2 ready and ready1 modes there are two states for the ready mode. the only difference between these states is the transition during start-up. the state ready1 mode ensures that the transition from ready to operation mode (once a rising edge of cs/wake) occurs without disrupting bus traffic. immediately upon entering either ready1 or ready mode, the voltage regulator will turn on and provide power. the transmitter portion of the circuit is off, with all other circuits (including the receiver) of the mcp201 being fully operational. the lin pin is kept in a recessive state. if a microcontroller is being driven by the voltage regulator output, it will go through a power-on reset and initialization sequence. all other circuits, other than the transmitter, are fully operational. the lin pin is held in the recessive state. the device will stay in ready mode until the cs/wake pin transitions high (? 1 ?). after cs/wake is active, the transmitter is enabled and the device enters operation mode. the device may only enter power-down mode after going through the operation mode step. at power-on of the v bat supply pin, the component is in either ready or ready1 mode, waiting for a cs/wake rising edge. the mcp201 will stay in either mode for 600 s as the regulator powers its internal circuitry and waits until the cs/wake pin transitions high. during the 600 s delay, the mcp201 will not recognize a cs/wake event. the cs/wake transition from low to high should not occur until after this delay. ? the cs input is edge, not level, sensitive. ? the cs pin is not monitored until approximately 600 s after v reg has stabized. ? the transistion from ready1 to ready is made on the falling edge of cs. ? the transition from ready mode to operational mode is on the rising edge of cs. 1.3.3 operation mode in this mode, all internal modules are operational. the mcp201 will go into power-down mode on the falling edge of cs/wake. figure 1-1: operational modes state diagrams 1.3.4 description of brownout conditions as v bat decreases v reg is regulated to 5.0 vdc (see v reg in section 2.2 ?dc specifications? ) while v bat is greater than 5.5 - 6.0 vdc. as v bat decreases further v reg tracks v bat (v reg = v bat - (0.5 to 1.0) vdc. the mcp201 monitors v reg and as long as v reg does not fall below v sd (see v sd in section 2.2 ?dc spec- ifications? ), v reg will remain powered. as v bat increases v reg will continue to track v bat until v reg reaches 5.0 vdc. if v reg falls below v sd , v reg is turned off and the mcp201 powers itself down. the mcp201 will remain powered down until v bat increases above v on (see v on in section 2.2 ?dc specifications? . note: after power-on, cs will not be sampled until v reg has stabized and an additional 600 s has elapsed. the microcontroller should toggle cs approximately 1ms after reset to ensure that cs will be recog- nized. note: while the mcp201 is in shutdown, txd should not be actively driven high. if txd is driven high actively, it may power internal logic. operation mode power-down mode ready mode bus activity cs/wake = true cs/wake = true por cs/wake = false ready1 mode cs/wake = true cs/wake = false cs/wake = false start f l t f l t
? 2007 microchip technology inc. ds21730f-page 5 mcp201 table 1-2: overview of operational modes state transmitter voltage regulator operation comments por off off read cs/wake. if low, then ready. if high, ready1 mode. sample fault/slps and select slope ready off on if cs/wake rising edge, then operation mode. bus off state ready1 off on if cs/wake falling edge, then ready mode. bus off state operation on on if cs/wake falling edge, then power down. normal operation mode power-down off off on lin bus falling, go to ready mode. on cs/wake rising edge, go to operational mode low-power mode note: after power-on, cs will not be sampled until v reg has stabized and an additional 600 s has elapsed. the microcontroller should toggle cs approximately 1ms after reset to ensure that cs will be recognized.
mcp201 ds21730f-page 6 ? 2007 microchip technology inc. 1.4 typical applications figure 1-2: typical mcp201 application (1,2) figure 1-3: typical lin network configuration lin bus d2 (4) v bat lin v reg txd rxd v ss v dd v ss txd rxd +5v pic ? +12v 10 uf c g cs/wake i/o fault /slps i/o 27v 1k +12v master node only +12v 10 k wake-up v reg or v ss 100 k optional components (5) optional components mcp201 c f d1 (3) note 1: the load capacitor, c g , should be a ceramic or tantalum rated for extended temperatures and be in the range of 1.0 - 22 f with an esr 0.4 - 5 . . 2: c f if the filter capacitor for the external voltage supply. 3: this diode is only needed if cs/wake is connected to 12v supply. 4: transient suppressor diode. vclamp l = 40v. 5: these components are for load dump protection. 24v mcu lin bus mcp201 master c 1k v bat slave 1 c slave 2 c slave n <16 c 40m + return lin bus lin bus mcp201 lin bus mcp201 lin bus mcp201
? 2007 microchip technology inc. ds21730f-page 7 mcp201 1.5 pin descriptions table 1-3: mcp201 pinout overview 1.5.1 receive data output (rxd) the receive data output pin is a standard cmos output and follows the state of the lin pin. the lin receiver monitors the state of the lin pin and generates the output signal rxd. 1.5.2 cs/wake chip select input pin. this pin controls whether the part goes into ready1 or ready mode at power-up. the internal pull-down resistor will keep the cs/wake pin low. this is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a power-on reset and i/o initialization sequence. the pin must see a low-to-high transition to activate the transmitter. after cs/wake transitions to ? 1 ?, the transmitter is enabled. if cs/wake = ? 0 ?, the device is in ready1 mode on power-up or in low-power mode. in low- power mode, the voltage regulator is shut down, the transmitter driver is disabled and the receiver logic is enabled. an external switch (see figure 1-2) can then wake up both the transceiver and the microcontroller. an external-blocking diode and current-limiting resistor are necessary to protect the microcontroller i/o pin. 1.5.3 power output (v reg ) positive supply voltage regulator output pin. 1.5.4 transmit data input (txd) the transmit data input pin has an internal pull-up to v reg . the lin pin is low (dominant) when txd is low, and high (recessive) when txd is high. in case the thermal protection detects an over-temper- ature condition while the signal txd is low, the transmitter is shutdown. the recovery from the thermal shutdown is equal to adequate cooling time. 1.5.5 ground (v ss ) ground pin. 1.5.6 lin the bidirectional lin bus interface pin is the driver unit for the lin pin and is controlled by the signal txd. lin has an open collector output with a current limitation. to reduce emi, the edges during the signal changes are slope-controlled. 1.5.7 battery (v bat ) battery positive supply voltage pin. this pin is also the input for the internal voltage regulator. 1.5.8 fault /slps fault detect output, slope select input. this pin is usually in output mode. its state is defined as shown in table 1-5. the state of this pin is internally sampled during power- on of v bat . once v bat has reached a stable level, (approximately 6 vdc) and v reg is stable at 4.75 to 5.25 vdc, the state of this pin selects which slew rate profile to apply to the lin output. it is only during this time that the pin is used as an input (the output driver is off during this time). the slope will stay selected until the next v bat power-off/power-on sequence, regard- less of any power-down, wake-up or sleep events. only a v bat rising state will cause a sampling of the fault /slps pin. the slope selection will be made irrespective of the state of any other pin. the fault /slps pin is connected to either v reg or v ss through a resistor (approximately 100 k ) to make the slope selection. this large resistance allows the fault indication function to overdrive the resistor in normal operation mode. if the fault /slps is high (? 1 ?), the normal slope shap- ing is selected (dv/dt = 2 v/s). if fault /slps is low (? 0 ?) during this time, the alternate slope-shaping is selected (dv/dt = 4 v/s). this mode can be used if a user desires to run at a faster slope. this mode is not lin compliant. devices bond pad name function 8-pin pdip/ soic/dfn normal operation 1 rxd receive data output (cmos output) 2 cs/wake chip select (ttl-hv input) 3v reg power output 4 txd transmit data input (ttl) 5v ss ground 6 lin lin bus (bidirectional- hv) 7v bat battery 8fault /slps fault detect output, slope select input legend: ttl = ttl input buffer, hv = high voltage (v bat ) note: on por, the mcp201 enters ready or ready1 mode (see figure 1-1). in order to enter operational mode, the mcp201 has to see one rising edge on cs/wake 600 s after the voltage regulator reaches 5v.
mcp201 ds21730f-page 8 ? 2007 microchip technology inc. table 1-4: fault / slps slope selection during por table 1-5: fault / slps truth table 1.6 internal voltage regulator the mcp201 has a low drop-out voltage, positive regulator capable of supplying 5.00 vdc 5% at up to 50 ma of load current over the entire operating temperature range. with a load current of 50 ma, the minimum input-to-output voltage differential required for the output to remain in regulation is typically +0.5v (+1v maximum over the full operating temperature range). quiescent current is less than 1.0 ma, with a full 50 ma load current, when the input-to-output voltage differential is greater than +2v. the regulator requires an external output bypass capacitor for stability. the capacitor should be either a ceramic or tantalum for stable operation over the extended temperature range. the compensation capacitor should range from 1.0 f ? 22 f and have a esr or csr of 0.4 ? 5.0 . the input capacitor, c f , in figure 1.4 should be on the order of 8 to 10 times larger than the output capacitor, c g . designed for automotive applications, the regulator will protect itself from reverse battery connections, double- battery jumps and up to +40v load dump transients. the voltage regulator has both short-circuit and thermal shutdown protection built-in. regarding the correlation between v bat , v reg and i dd , please refer to figure 1-4 through 1-6. when the input voltage (v bat ) drops below the differential needed to provide stable regulation, the output v reg will track the input down to approximately 3.5v, at which point the regulator will turn off. this will allow microcontrollers with internal por circuits to generate a clean arming of the power-on reset trip point. the mcp201 will then monitor v bat and turn on the regulator when v bat is 6.0v. the device will come up in either ready1 or ready mode and will have to be transitioned to operational mode to re-enable data transmission. in the start phase, v bat must be at least 6.0v (figure 1-4) to initiate operation during power-up. in power-down mode, the v bat monitor will be turned off. the regulator has a thermal shutdown. if the thermal protection circuit detects an overtemperature condition caused by an overcurrent condition (figure 1-6) of the regulator, it will shut down. the regulator has an overload current limiting. during a short-circuit, v reg is monitored. if v reg is lower than 3.5v, the regulator will turn off. after a thermal recovery time, the v reg will be checked again. if there is no short-circuit (v reg > 3.5v), the regulator will be switched back on. the mcp201 will come up in either ready1 or ready mode and will have to be transitioned to operational mode to re-enable data transmission. the accuracy of the voltage regulator, when using a pass transistor, will degrade due to the extra external components needed. all performance characteristics should be evaluated on every design. fault /slps slope shaping hnormal lalternate (1) note 1: this mode does not conform to lin bus specification version 1.3, but might be used for k-line applications. note: this pin is ? 0 ? whenever the internal circuits have detected a short or thermal excursion and have disabled the lin output driver. note: every time tx is toggled, a fault condition will occur for the length of time, depending on the bus load. the fault time is equal to the propagation delay. txd in rxd out lin bus i/o thermal override fault / slps out comments lhv bat off l bus shorted to battery hhv bat off h bus recessive l l gnd off h bus dominant h l gnd off l bus shorted to ground xxv bat on l thermal excursion legend: x = don?t care
? 2007 microchip technology inc. ds21730f-page 9 mcp201 figure 1-4: voltage regulator output on power-on reset note 1: start-up, v bat < 6.0v, regulator off. 2: v bat > 6.0v, regulator on. 3: v bat 5.5v, regulator tracks v bat , regulator will turn off when v reg < 3.5v. 5.5 3.5 3 0 v reg v -------------- - (1) (2) (3) t 0 t 6 2 8 4 v bat v ------------- -
mcp201 ds21730f-page 10 ? 2007 microchip technology inc. figure 1-5: voltage regulator output on power dip note 1: voltage regulator on. 2: v reg 5.5v, regulator tracks v bat until v reg < 3.5v. 3: v reg < 3.5v, regulator is off. if the voltage regulator should shut off due to v reg falling below 3.5v, the v bat must rise to 6.0v to turn v reg back on. 4: v reg > 4.0v, voltage regulator tracks v dd , when v reg > 4.0v. 5 3.5 3 0 v reg v -------------- - (1) (2) (3) t 0 t 6 2 8 4 3.5 v bat v ------------- - 12 (4) 4
? 2007 microchip technology inc. ds21730f-page 11 mcp201 figure 1-6: voltage regulator output on overcurrent situation 1.7 icsp? considerations the following should be considered when the mcp201 is connected to pins supporting in-circuit programming: ? power used for programming the microcontroller should be supplied from the programmer, not from the mcp201 ? the mcp201 should be left unpowered ? the voltage on v reg should not exceed the maximum output voltage of v reg ? the txd pin should not be brought high during programming note 1: i reg less than 50 ma, regulator on. 2: after i reg exceeds i reg max, voltage regulator output will be reduced until v reg off is reached. 5 3.5 3 0 v reg v -------------- - (1) (2) t 0 t 50 6 i reg ma ------------ -
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? 2007 microchip technology inc. ds21730f-page 13 mcp201 2.0 electrical characteristics 2.1 absolute maximum ratings? v in dc voltage on logic pins except cs/wake ................................................................................. -0.3 t o v reg +0.3v v in dc voltage on cs/wake ......................................................................................................... ......-0.3 to v bat +0.3v v bat battery voltage, non-operating (lin bus recessive, no regulator load, t < 60s)....................................-0.3 to +40v v bat battery voltage, transient ( note 1 )........................................................................................................-0.3 to +40v v bat battery voltage, continuous ................................................................................................... ...............-0.3 to +30v v lbus bus voltage, continuous....................................................................................................... ................-18 to +30v v lbus bus voltage, transient ( note 1 )............................................................................................................-27 to +40v i lbus bus short circuit current limit ............................................................................................... .....................200 ma esd protection on lin, v bat (human body model) ( note 2 ) .................................................................................. >4 kv esd protection on all other pins (human body model) ( note 2 ) ............................................................................. >2 kv maximum junction temperature ................................................................................................... .......................... 150 c storage temperature ............................................................................................................ ...................... -55 to +150 c note 1: iso 7637/1 load dump compliant (t < 500 ms). 2: according to jesd22-a114-b. ? notice : stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
mcp201 ds21730f-page 14 ? 2007 microchip technology inc. 2.2 dc specifications dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bat = 6.0v to 18.0v t amb = -40c to +125c c loadreg = 10 f sym. parameter min. typ. max. units conditions power i batq v bat quiescent operating current (voltage regulator without load and transceiver) ? 0.45 1.0 ma i vreg = 0 ma, lin bus pin recessive, (note 3) i bat v bat power-down current transceiver only ? 23 50 a cs/wake = high, voltage regulator disabled i ddq v reg quiescent operating current ?500 ? a (note 2) i vreg v reg maximum output current ?? 50 ma (note 4) microcontroller interface v ih high-level input voltage (txd, fault /slps) 2.0 ? v reg + 0.3 v v il low-level input voltage (txd, fault /slps) -0.3 ? 0.15 x v reg v i ihtxd high-level output current (txd) -90 ? +30 a input voltage = 4v i iltxd low-level output current (txd) -150 ? -10 a input voltage = 1v (though > 50 k internal pull-up) v ihcs / wake high-level input voltage (cs/wake) 3.0 ? v bat v through an external current- limiting resistor (10 k ) v ilcs / wake low-level input voltage (cs/wake) -0.3 ? 1.0 v i ihcs / wake high-level input current (cs/wake) -10 ? +80 a input voltage = 4v (though >100 k internal pull-down) i ilcs / wake low-level input current (cs/wake) 5 ? 30 a input voltage = 1v v ohrxd high-level output voltage (rxd) 0.8 v reg ?? i oh = -4 ma v olrxd low-level output voltage (rxd) ??0.2 v reg i ol = 4 ma note 1: internal current limited. 2.0 ms typical recovery time (r lbus = 0 , tx = 0.4 v reg , v lbus = v bat , t amb = 25c. recovery time highly dependent on ambient temperature, package and thermal resistance). 2: for design guidance only, not tested. 3: this current is at the v bat pin. 4: the maximum power dissipation is a function of t jmax , ja and ambient temperature t a . the maximum allowable power dissipation at an ambient temperature is p d = (t jmax - t a ) ja . if this dissipation is exceeded, the die temperature will rise above 150 c and the mcp201 will go into thermal shutdown.
? 2007 microchip technology inc. ds21730f-page 15 mcp201 bus interface v ihlbus high-level input voltage (l bus ) 0.6 v bat ? 18 v recessive state v illbus low-level input voltage (l bus ) -8 ? 0.4 v bat v dominant state v hys input hysteresis 0.05 v bat ? 0.1 v bat vv ih - v il i ol low-level output current (l bus ) 40 ? 200 ma output voltage = 0.1 v bat , v bat = 12v i o high-level output current (l bus ) -20 ? 20 a v bus v bat , v lbus < 40v i p pull-up current on input (l bus ) -180 ? -60 a approx. 30 k internal pull-up @ v ih = 0.7 v bat i sc short-circuit current-limit 50 ? 200 ma (note 1) v oh high-level output voltage (l bus ) 0.8 v bat ?? v v ol low-level output voltage (l bus ) ??0.2 v bat v voltage regulator v reg output voltage 4.75 ? 5.25 v 0 ma > i out > 50 ma, 7.0v < v bat < 18v v reg 1 output voltage 4.4 ? 5.25 v 0 ma > i out > 50 ma, 6.0v < v bat < 7.0v v reg 1 line regulation ? 10 50 mv i out = 1 ma, 7.0v < v bat < 18v v reg 2 load regulation ? 10 50 mv 5 ma < i out < 50 ma, v bat = constant v n output noise voltage ? ? 400 v rms 1v rms @ 10 hz - 100 khz v sd shutdown voltage (monitoring v reg ) 3.5 ? 4.0 v see figure 1-4 v on input voltage to turn on output (monitoring v bat ) 5.5 ? 6.0 v 2.2 dc specifications (continued) dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bat = 6.0v to 18.0v t amb = -40c to +125c c loadreg = 10 f sym. parameter min. typ. max. units conditions note 1: internal current limited. 2.0 ms typical recovery time (r lbus = 0 , tx = 0.4 v reg , v lbus = v bat , t amb = 25c. recovery time highly dependent on ambient temperature, package and thermal resistance). 2: for design guidance only, not tested. 3: this current is at the v bat pin. 4: the maximum power dissipation is a function of t jmax , ja and ambient temperature t a . the maximum allowable power dissipation at an ambient temperature is p d = (t jmax - t a ) ja . if this dissipation is exceeded, the die temperature will rise above 150 c and the mcp201 will go into thermal shutdown.
mcp201 ds21730f-page 16 ? 2007 microchip technology inc. 2.3 ac specifications table 2-1: mcp201 thermal specifications ac specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bat = 6.0v to 18.0v t amb = -40c to +125c symbol parameter min typical max units conditions bus interface |dv/dt| slope rising and falling edges 1.0 2.0 3.0 v/ s (40% to 60%), no load |dv/dt| slope rising and falling edges alternate 2.0 4.0 6.0 v/ s( note 1 ), no load t transpd propagation delay of transmitter ? ? 6.0 st recpd = max t recpd propagation delay of receiver ? ? 6.0 s(t recpdr or t recpdf ) t recsym symmetry of propagation delay of receiver rising edge with respect to falling edge -2.0 ? 2.0 st recsym = max t transsym symmetry of propagation delay of transmitter rising edge with respect to falling edge -2.0 ? 2.0 st transsym = max (t transpdf - t ranspdr ) voltage regulator t bactve bus activity to voltage regulator enabled 10 ? 40 s bus debounce time t vevr voltage regulator enabled to ready ?50200 s (note 2) t vregpo r voltage regulator enabled to ready after por ??2.5ms (note 2) c load = 25 nf t csor chip select to operation ready 0 50 200 s (note 2) t cspd chip select to power-down 0 ? 40 s (note 2) no c load t shutdown short-circuit to shutdown ? 450 ? s characterized but not tested t screc short-circuit recovery time ? 2.0 ? ms characterized but not tested (note 3) note 1: the mode does not conform to lin bus specification version 1.3. 2: time depends on external capacitance and load. 3: internal current limited. 2.0 ms typical recovery time (r lbus = 0 , tx = 0.4 v reg , v lbus = v bat , t amb = 25c. recovery time highly dependent on ambient temperature, package, and thermal resistance). sym parameter min typical max units test conditions recovery recovery temperature (junction temperature) ?+135? c characterized but not tested shutdown shutdown temperature (junction temperature) ?+155? c characterized but not tested t therm thermal recovery time (after fault condition removed) ? 2.0 ? ms characterized but not tested (note 1) note 1: internal current limited. 2.0 ms typical recovery time (r lbus = 0 , tx = 0.4 v reg , v lbus = v bat , t amb = 25c. recovery time highly dependent on ambient temperature, package, and thermal resistance).
? 2007 microchip technology inc. ds21730f-page 17 mcp201 2.4 timing diagrams and specifications figure 2-1: bus timing diagram figure 2-2: regulator timing diagram on cs/wake signal .6 v bat .4 v bat t transpdr t recpdr t transpdf t recpdf txd l bus rxd t cspd t csor cs/wake v reg regulator stable
mcp201 ds21730f-page 18 ? 2007 microchip technology inc. figure 2-3: regulator timing diagram on bus activity figure 2-4: por diagram l bus .4 v bat t vevr t bactve v reg regulator stable v reg t vregpor v bat 6v 5.0v
? 2007 microchip technology inc. ds21730f-page 19 mcp201 3.0 characterization graphs figure 3-1: i dd (ma) vs. v bat t cspd (s) vs. v bat (v) t cspd (s) 0 100 200 300 400 500 600 700 4 6 8 10 12 14 16 18 20 t cspd (s) -40(c) t cspd (s) 125(c) t cspd (s) 25(c) v bat (v) dap/jx 3/5/03 30 parts y1004 b2
mcp201 ds21730f-page 20 ? 2007 microchip technology inc. figure 3-2: regulator voltage (v) vs. regulator current v regout (v) v bat 18(v) -40(c) v regout (v) v bat 14.4(v) -40(c) v regout (v) v bat 8(v) -40(c) v regout (v) v bat 6(v) -40(c) v regout (v) v bat 18(v) 25(c) v regout (v) v bat 14.4(v) 25(c) v regout (v) v bat 8(v) 25(c) v regout (v) v bat 6(v) 25(c) v regout (v) v bat 18(v) 125(c) v regout (v) v bat 14.4(v) 125(c) v regout (v) v bat 8(v) 125(c) v regout (v) v bat 6(v) 125(c) regulator voltage (v) regulator current (ma) 5.25 5.15 5.05 4.95 4.85 4.75 4.65 4.45 4.55 4.35 4.25 0 102030405060 dap/jx 2/28/03 30 parts y1004 b2 regulator voltage (v) vs. regulator current (a)
? 2007 microchip technology inc. ds21730f-page 21 mcp201 figure 3-3: regulator change (v) vs. line voltage change regulator change (mv) -40(c) load = 50(ma) regulator change (mv) -40(c) load = 25(ma) regulator change (mv) -40(c) load = 1(ma) regulator change (mv) 25(c) load = 25(ma) regulator change (mv) 125(c) load = 50(ma) regulator change (mv) 125(c) load = 25(ma) regulator change (mv) 125(c) load = 5(ma) regulator change (mv) 125(c) load = 1(ma) regulator change (mv) 25(c) load = 5(ma) regulator change (mv) 25(c) load = 1(ma) regulator change (mv) 25(c) load = 50(ma) regulator change (mv) -40(c) load = 5(ma) line regulation regulator change (v) vs line voltage change (mv) line voltage change (v) regulator change (mv) 5 0 -5 -10 -15 -20 -25 -30 -35 -40 0 2 4 6 8 10 12 14 dap/jx 3/3/03 30 parts y1004 b2
mcp201 ds21730f-page 22 ? 2007 microchip technology inc. figure 3-4: load regulation regulator change vs. regulator load change load regulation regulator change (mv) vs. regulator load change (ma) re g ular load current chan g e ( ma ) regular charge (mv) 0 102030405060 dap/jx 3/3/03 30 parts y1004 b2 regulator change (mv) -40c v bat = 14.4v regulator change (mv) 125c v bat = 18v regulator change (mv) 125c v bat = 14.4v regulator change (mv) 125c v bat = 8.0v regulator change (mv) 125c v bat = 6.0v regulator change (mv) 25c v bat = 6.0v regulator change (mv) 25c v bat = 8.0v regulator change (mv) 25c v bat = 14.4v regulator change (mv) 25c v bat = 18v regulator change (mv) -40c v bat = 6.0v regulator change (mv) -40c v bat = 8.0v regulator change (mv) -40c v bat = 18v 70 60 50 40 30 20 10 0
? 2007 microchip technology inc. ds21730f-page 23 mcp201 figure 3-5: falling edge normal dv/dt vs. vbat falling edge normal dvdt (v/s) vs. v bat (v) falling edge normal dvdt (v/s) 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 4 6 8 10 12 14 16 18 20 falling edge normal dvdt (v/s) -40(c) falling edge normal dvdt (v/s) 25(c) falling edge normal dvdt (v/s) 125(c) v bat (v) dap/jx 3/6/03 30 parts y1004 b2
mcp201 ds21730f-page 24 ? 2007 microchip technology inc. figure 3-6: rising edge normal dv/dt vs. vbat rising edge normal dv/dt (v/s) vs. v bat (v) rising edge normal dv/dt (v/s) 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 4 6 8 101214161820 rising edge normal dvdt (v/s) -40(c) rising edge normal dvdt (v/s) 125(c) rising edge normal dvdt (v/s) 25(c) dap/jx 3/6/03 30 parts y1004 b2 v bat (v)
? 2007 microchip technology inc. ds21730f-page 25 mcp201 figure 3-7: bus active vs. vbat t bactive (s) vs. v bat (v) 20 18 16 14 12 10 8 6 4 30 35 40 45 50 55 tbactive (s) -40(c) tbactive (s) 25(c) tbactive (s) 125(c) dap/jx 3/6/03 30 parts y1004 b2 v bat (v) t bactive (s)
mcp201 ds21730f-page 26 ? 2007 microchip technology inc. figure 3-8: voltage regulator active time vs. vbat t vevr (s) vs. v bat (v) t vevr (s) 10000 1000 100 10 4 6 8 10 12 14 16 18 20 10 t vevr (s) -40(c) t vevr (s) 25(c) t vevr (s) 125(c) v bat (v) dap/jx 3/6/03 30 parts y1004 b2
? 2007 microchip technology inc. ds21730f-page 27 mcp201 figure 3-9: chip select to operation ready t csor (s) vs. v bat (v) t csor (s) 14 13 12 11 10 9 8 7 6 5 4 20 18 16 14 12 10 8 6 4 t csor (s) -40(c) t csor (s) 125(c) t csor (s) 25(c) v bat (v) dap/jx 3/5/03 30 parts y1004 b2
mcp201 ds21730f-page 28 ? 2007 microchip technology inc. figure 3-10: chip select to power down t cspd (s) vs. v bat (v) t cspd (s) 0 100 200 300 400 500 600 700 4 6 8 10 12 14 16 18 20 t cspd (s) -40(c) t cspd (s) 125(c) t cspd (s) 25(c) v bat (v) dap/jx 3/5/03 30 parts y1004 b2
? 2007 microchip technology inc. ds21730f-page 29 mcp201 figure 3-11: propagation delay of transmitter t transpd (s) rising edge normal vs. v bat (v) 1.8 1.7 1.6 1.5 1.9 2 2.1 2.2 2.3 2.4 2.5 4 6 8 10 12 14 16 18 20 t transpd (s) rising edge normal -40(c) t transpd (s) rising edge normal 25(c) t transpd (s) rising edge normal 125(c) v bat (v) dap/jx 3/6/03 30 parts y1004 b2 t transpd (s) rising edge normal
mcp201 ds21730f-page 30 ? 2007 microchip technology inc. figure 3-12: propagation delay of receiver t recpd (s) falling edge normal vs. v bat (v) 1.9 1.7 1.5 2.1 2.3 2.5 2.7 2.9 3.1 3.3 4 6 8 10 12 14 16 18 20 t recpd (s) falling edge normal -40(c) t recpd (s) falling edge normal 25(c) t recpd (s) falling edge normal 125(c) v bat (v) dap/jx 3/6/03 30 parts y1004 b2 t recpd (s) falling edge normal
? 2007 microchip technology inc. ds21730f-page 31 mcp201 4.0 packaging information 4.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn e/p256 0715 mcp201 e/sn0715 256 mcp201 8-lead dfn-s example : xxxxxxxx xxxxxxxx yyww nnn mcp201 e/mf 0715 256 3 e 3 e 3 e
mcp201 ds21730f-page 32 ? 2007 microchip technology inc. 8-lead plastic dual flat, no lead package (mf) ? 6x5 mm body [dfn-s] p unch singulated n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . package may have one or more exposed tie bars at ends. 3 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a ? 0.85 1.00 molded package thickness a2 ? 0.65 0.80 standoff a1 0.00 0.01 0.05 base thickness a3 0.20 ref overall length d 4.92 bsc molded package length d1 4.67 bsc exposed pad length d2 3.85 4.00 4.15 overall width e 5.99 bsc molded package width e1 5.74 bsc exposed pad width e2 2.16 2.31 2.46 contact width b 0.35 0.40 0.47 contact length l 0.50 0.60 0.75 contact-to-exposed pad k 0.20 ? ? model draft angle top ? ? 12 n o te 2 a3 a2 a1 a n o te 1 n o te 1 ex pos e d pad bo tt o m v iew 1 2 d2 2 1 e 2 k l n e b e e 1 d d1 n t op v iew microchip technology drawing c04-113 b
? 2007 microchip technology inc. ds21730f-page 33 mcp201 8-lead plastic dual in-line (p) ? 300 mil body [pdip] n otes: 1 . pin 1 visual index feature may vary, but must be located with the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 8 pitch e .100 bsc top to seating plane a ? ? .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .348 .365 .400 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 n e 1 n o te 1 d 12 3 a a1 a2 l b 1 b e e eb c
mcp201 ds21730f-page 34 ? 2007 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 3.90 mm body [soic] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millmeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a ? ? 1.75 molded package thickness a2 1.25 ? ? standoff a1 0.10 ? 0.25 overall width e 6.00 bsc molded package width e1 3.90 bsc overall length d 4.90 bsc chamfer (optional) h 0.25 ? 0.50 foot length l 0.40 ? 1.27 footprint l1 1.04 ref foot angle 0 ? 8 lead thickness c 0.17 ? 0.25 lead width b 0.31 ? 0.51 mold draft angle top 5 ? 15 mold draft angle bottom 5 ? 15 d n e e e 1 n o te 1 12 3 b a a1 a2 l l 1 c h h microchip technology drawing c04-057 b
? 2007 microchip technology inc. ds21730f-page 35 mcp201 appendix a: revision history revision f (january 2007) this revision includes updates to the packaging diagrams.
mcp201 ds21730f-page 36 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21730f-page 37 mcp201 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx package temperature range device device: mcp201: lin transceiver with voltage regulator mcp201t: lin transceiver with voltage regulator (tape and reel) temperature range: i = -40c to +85c e = -40c to +125c package: mf = dual flatpack, no-lead (6x5 mm body), 8-lead p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead examples: a) mcp201-e/sn: extended temperature, soic package. b) mcp201-e/p: extended temperature, pdip package. c) mcp201-i/sn: industrial temperature, soic package. d) mcp201-i/p: industrial temperature, pdip package. e) mcp201t-i/sn: tape and reel, industrial temperature, soic package. f) mcp201t-e/sn: tape and reel, extended temperature, soic package. g) mcp201-e/mf: extended temperature, dfn package. h) mcp201t-e/mf: tape and reel, extended temperature, dfn package.
mcp201 ds21730f-page 38 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds21730f-page 39 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mindi, miwi, mpasm, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powe rtool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? mcus and dspic dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
ds21730f-page 40 ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway habour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7250 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - gumi tel: 82-54-473-4301 fax: 82-54-473-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 12/08/06

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